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M.Tech-ECE-VLSI 2018-2019

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Projects List

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Base Paper

Abstract

1. Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter Front End 2018 Download Download
2. An Efficient VLSI Architecture for Convolution Based DWT Using MAC Front End 2018 Download Download
3. VLSI Design Of Low-Cost And High-Precision Fixed-Point Reconfigurable FFT Processors Front End 2018 Download Download
4. FIR Filter Design Based On FPGA Front End 2018 Download Download
5. Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters Front End 2018 Download Download
6. A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation Front End 2018 Download Download
7. An Approach to LUT Based Multiplier for Short Word Length DSP Systems Front End 2018 Download Download
8. EEG Signal Denoising based on Wavelet Transform using Xilinx System Generator Front End 2018 Download Download
9. Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary Signed Digit number system Front End 2018 Download Download
10. FPGA Implementation of an Improved Watchdog Timer for Safety-critical Applications Front End 2018 Download Download
11. Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption Front End 2018 Download Download
12. Unbiased Rounding for HUB Floating-point Addition Front End 2018 Download Download
13. A Low-Power Yet High-Speed Configurable Adder for Approximate Computing Front End 2018 Download Download
14. A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design Front End 2018 Download Download
15. The Design and Implementation of Multi – Precision Floating Point Arithmetic Unit Based on FPGA Front End 2018 Download Download
16. Chip Design for Turbo Encoder Module for In-Vehicle System Front End 2018 Download Download
17. Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction Front End 2018 Download Download
18. Low-power Implementation of Mitchell's Approximate Logarithmic Multiplication for Convolutional Neural Networks Front End 2018 Download Download
19. Efficient Modular Adders based on Reversible Circuits Front End 2018 Download Download
20. High Performance Division Circuit using Reversible Logic Gates Front End 2018 Download Download
21. Power Efficient Approximate Multipliers in LMS Adaptive Filters Front End 2018 Download Download
22. MAES: Modified Advanced Encryption Standard for Resource Constraint Environments Front End 2018 Download Download
23. Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers Front End 2018 Download Download
24. Binary To Gray Code Converter Implementation Using QCA Front End 2018 Download Download
25. A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA) Front End 2018 Download Download
26. A Novel Five-input Multiple-function QCA Threshold Gate Front End 2018 Download Download
27. A Low-Power High-Speed Comparator for Precise Applications Back End 2018 Download Download
28. A High Performance Gated Voltage Level Translator with Integrated Multiplexer Back End 2018 Download Download
29. Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates Back End 2018 Download Download
30. Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications Back End 2018 Download Download
31. High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop Back End 2018 Download Download
32. Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder Back End 2018 Download Download
33. Fractional- Order Differentiators and Integrators with Reduced Circuit Complexity Back End 2018 Download Download
34. Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis Back End 2018 Download Download
35. Hardware Implementation Of Polyphone-Decomposition-Based Wavelet Filters For Power System Harmonics Estimation Front End 2017 Download Download
36. A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations Front End 2017 Download Download
37. Operating Frequency Improvement On FPGA Implementation Of A Pipeline Large-FFT Processor Front End 2017 Download Download
38. High Performance Integer DCT Architectures for HEVC Back End 2017 Download Download
39. Design of Efficient Programmable Test-per-Scan Logic BIST Modules Front End 2017 Download Download
40. A Residue-to-Binary Converter for the Extended Four-Moduli Set {2n - 1, 2n + 1, 22n + 1, 22n+p} Front End 2017 Download Download
41. Design and Analysis of Multiplier Using Approximate 15-4 Compressor Front End 2017 Download Download
42. Probability-Driven Multibit Flip-Flop Integration With Clock Gating Front End 2017 Download Download
43. Area-Time Efficient Architecture of FFT-Based Montgomery Multiplication Front End 2017 Download Download
44. Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA Front End 2017 Download Download
45. Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction Front End 2017 Download Download
46. Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs Front End 2017 Download Download
47. An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA Front End 2017 Download Download
48. RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing Front End 2017 Download Download
49. DLAU: A Scalable Deep Learning Accelerator Unit on FPGA Front End 2017 Download Download
50. Design of Efficient BCD Adders in Quantum-Dot Cellular Automata Front End 2017 Download Download
51. Overloaded CDMA Crossbar for Network-On-Chip Front End 2017 Download Download
52. Design of Power and Area Efficient Approximate Multipliers Front End 2017 Download Download
53. Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST Front End 2017 Download Download
54. Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication Front End 2017 Download Download
55. Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders. Back End 2017 Download Download
56. Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit Back End 2017 Download Download
57. 12T Memory Cell for Aerospace Applications in Nano scale CMOS Technology Back End 2017 Download Download
58. Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding Front End 2016 Download Download
59. Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic Front End 2016 Download Download
60. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication Front End 2016 Download Download
61. A High-Speed FPGA Implementation of an RSD-Based ECC Processor Front End 2016 Download Download
62. Hybrid LUT/Multiplexer FPGA Logic Architectures Front End 2016 Download Download
63. In-Field Test for Permanent Faults in FIFO Buffers of NOC Routers Front End 2016 Download Download
64. Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design Back End 2016 Download Download
65. A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell Back End 2016 Download Download