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M.Tech-ECE-VLSI 2019-2020

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Projects List

Design

IEEE

Base Paper

Abstract

1. A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories Front End 2019 Download Download
2. Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications Front End 2019 Download Download
3. Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms Front End 2019 Download Download
4. TOSAM:AnEnergy-EfficientTruncation-andRounding-BasedScalableApproximate Multiplier Front End 2019 Download Download
5. Design And Analysis Of Approximate Redundant Binary Multipliers. Front End 2019 Download Download
6. Rounding Technique Analysis Of Power-Area & Energy Efficient Approximate Multiplier Design Front End 2019 Download Download
7. A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapath. Front End 2019 Download Download
8. Low Power High Accuracy Approximate Multiplier Using Approximate High Order Compressors. Front End 2019 Download Download
9. Efficient Modular Adder Designs Based on Thermometer & One-Hot Encoding Front End 2019 Download Download
10. Error Detection And Correction In SRAM Emulated TCAMs Front End 2019 Download Download
11. Efficient Design For Fixed Width Adder Tree Front End 2019 Download Download
12. Area –Time Efficient Streaming Architecture For Architecture For FAST And BRIEF Detector Front End 2019 Download Download
13. Hard Ware Efficient Post Processing Architecture For True Random Number Generators Front End 2019 Download Download
14. A Two Speed Radix -4 Serial –Parallel Multiplier Front End 2019 Download Download
15. Low power approximate unsigned multipliers with configurable error recovery Front End 2019 Download Download
16. Energy Quality Scalable Adders Based On Non Zeroing Bit Truncation Front End 2019 Download Download
17. Double MAC On A DSP Boosting The Performance Of Convolutional Neural Networks On FPGAS Front End 2019 Download Download
18. A Low-Power Parallel Architecture for Linear Feedback Shift Registers Front End 2019 Download Download
19. Ultra-low-voltage GDI-based hybrid full adder design for area and energy-efficient computing systems Back End 2019 Download Download
20. Design Of Area Efficient And Low Power 4-Bit Multiplier Based On Full- swing GDI technique Back End 2019 Download Download
21. Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications Back End 2019 Download Download
22. Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS Back End 2019 Download Download
23. Column selection enabled 10 T SRAM utilizing shared diff VDD WRITE and dropped VDD read for FFT on real data. Back End 2019 Download Download
24. Cell-state-distribution –assisted threshold voltage detector for NAND flash memory Back End 2019 Download Download
25. Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino Logic Back End 2019 Download Download
26. An Approach to LUT Based Multiplier for Short Word Length DSP Systems Front End 2018 Download Download
27. Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary Signed Digit number system Front End 2018 Download Download
28. FPGA Implementation of an Improved Watchdog Timer for Safety-critical Applications Front End 2018 Download Download
29. Unbiased Rounding for HUB Floating-point Addition Front End 2018 Download Download
30. A Low-Power Yet High-Speed Configurable Adder for Approximate Computing Front End 2018 Download Download
31. A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design Front End 2018 Download Download
32. The Design and Implementation of Multi – Precision Floating Point Arithmetic Unit Based on FPGA Front End 2018 Download Download
33. Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction Front End 2018 Download Download
34. Efficient Modular Adders based on Reversible Circuits Front End 2018 Download Download
35. MAES: Modified Advanced Encryption Standard for Resource Constraint Environments Front End 2018 Download Download
36. Chip Design for Turbo Encoder Module for In-Vehicle System Front End 2018 Download Download
37. Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates Back End 2018 Download Download
38. Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder Back End 2018 Download Download
39. Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis Back End 2018 Download Download
40. Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction Front End 2017 Download Download
41. Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs Front End 2017 Download Download
42. An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA Front End 2017 Download Download
43. RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing Front End 2017 Download Download
44. DLAU: A Scalable Deep Learning Accelerator Unit on FPGA Front End 2017 Download Download
45. Overloaded CDMA Crossbar for Network-On-Chip Front End 2017 Download Download
46. Design of Power and Area Efficient Approximate Multipliers Front End 2017 Download Download
47. Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST Front End 2017 Download Download
48. Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders. Back End 2017 Download Download
49. Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit Back End 2017 Download Download
50. 12T Memory Cell for Aerospace Applications in Nano scale CMOS Technology Back End 2017 Download Download
51. Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding Front End 2016 Download Download
52. Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic Front End 2016 Download Download
53. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication Front End 2016 Download Download
54. A High-Speed FPGA Implementation of an RSD-Based ECC Processor Front End 2016 Download Download
55. Hybrid LUT/Multiplexer FPGA Logic Architectures Front End 2016 Download Download
56. In-Field Test for Permanent Faults in FIFO Buffers of NOC Routers Front End 2016 Download Download