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M.Tech-ECE-VLSI 2017-2018

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Projects List

Design

IEEE

Base Paper

Abstract

1. A Bit-Plane Decomposition Matrix-Based VLSI Integer Transform Architecture for HEVC Front End 2017 Download Download
2. Probability-Driven Multibit Flip-Flop Integration With Clock Gating Front End 2017 Download Download
3. Area-Time Efficient Architecture of FFT-Based Montgomery Multiplication Front End 2017 Download Download
4. Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA Front End 2017 Download Download
5. Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction Front End 2017 Download Download
6. A Structured Visual Approach to GALS Modeling and Verification of Communication Circuits Front End 2017 Download Download
7. Weighted Partitioning for Fast Multiplierless Multiple-Constant Convolution Circuit Front End 2017 Download Download
8. Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials Front End 2017 Download Download
9. Probabilistic Error Modeling for Approximate Adders Front End 2017 Download Download
10. LFSR-Based Generation of Multicycle Tests Front End 2017 Download Download
11. Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs Front End 2017 Download Download
12. An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA Front End 2017 Download Download
13. RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing Front End 2017 Download Download
14. DLAU: A Scalable Deep Learning Accelerator Unit on FPGA Front End 2017 Download Download
15. A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices Front End 2017 Download Download
16. Design of Efficient Multiplierless Modified Cosine-Based Comb Decimation Filters: Analysis and Implementation Front End 2017 Download Download
17. Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping Front End 2017 Download Download
18. Design of Efficient BCD Adders in Quantum-Dot Cellular Automata Front End 2017 Download Download
19. Overloaded CDMA Crossbar for Network-On-Chip Front End 2017 Download Download
20. High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder Front End 2017 Download Download
21. Design of Power and Area Efficient Approximate Multipliers Front End 2017 Download Download
22. An Efficient O(N) Comparison-Free Sorting Algorithm Front End 2017 Download Download
23. Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems Front End 2017 Download Download
24. A General Digit-Serial Architecture for Montgomery Modular Multiplication Front End 2017 Download Download
25. High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations Front End 2017 Download Download
26. Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST Front End 2017 Download Download
27. Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication Front End 2017 Download Download
28. A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes. Front End 2017 Download Download
29. On the VLSI Energy Complexity of LDPC Decoder Circuits Front End 2017 Download Download
30. Reconfigurable Constant Multiplication for FPGAs Front End 2017 Download Download
31. LLR-Based Successive-Cancellation List Decoder for Polar Codes With Multibit Decision Front End 2017 Download Download
32. Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division Front End 2017 Download Download
33. Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields Front End 2017 Download Download
34. Dual-Quality 4: 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers Back End 2017 Download Download
35. Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique Back End 2017 Download Download
36. Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders. Back End 2017 Download Download
37. Register-Less NULL Convention Logic. Back End 2017 Download Download
38. Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops Back End 2017 Download Download
39. Delay Analysis for Current Mode Threshold Logic Gate Designs Back End 2017 Download Download
40. 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage Back End 2017 Download Download
41. Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding Front End 2016 Download Download
42. Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation Front End 2016 Download Download
43. Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic Front End 2016 Download Download
44. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Front End 2016 Download Download
45. A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits Front End 2016 Download Download
46. On Efficient Retiming of Fixed-Point Circuits Front End 2016 Download Download
47. Concept, Design, and Implementation of Reconfigurable CORDIC Front End 2016 Download Download
48. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks Front End 2016 Download Download
49. Low-Power Parallel Chien Search Architecture Using a Two-Step Approach Front End 2016 Download Download
50. An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code Front End 2016 Download Download
51. Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression Front End 2016 Download Download
52. Multiple Constant Multiplication Algorithm for High-Speed and Low-Power Design Front End 2016 Download Download
53. Design and Analysis of Inexact Floating-Point Adders Front End 2016 Download Download
54. A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT Front End 2016 Download Download
55. A Modified Partial Product Generator for Redundant Binary Multipliers Front End 2016 Download Download
56. A Cellular Network Architecture With Polynomial Weight Functions Front End 2016 Download Download
57. A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO Front End 2016 Download Download
58. High Speed Hybrid Double Multiplication Architectures Using New Serial-Out Bit- Level Mastrovito Multipliers Front End 2016 Download Download
59. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication Front End 2016 Download Download
60. A High-Speed FPGA Implementation of an RSD-Based ECC Processor Front End 2016 Download Download
61. VLSI Design for Convolutive Blind Source Separation Front End 2016 Download Download
62. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels Front End 2016 Download Download
63. Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding Front End 2016 Download Download
64. Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers Front End 2016 Download Download
65. Hybrid LUT/Multiplexer FPGA Logic Architectures Front End 2016 Download Download
66. High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m) Front End 2016 Download Download
67. In-Field Test for Permanent Faults in FIFO Buffers of NOC Routers Front End 2016 Download Download
68. Performance/Power Space Exploration for Binary64 Division Units Front End 2016 Download Download
69. A High Throughput List Decoder Architecture for Polar Codes Front End 2016 Download Download
70. A Novel Coding Scheme for Secure Communications in Distributed RFID Systems Front End 2016 Download Download
71. Arithmetic algorithms for extended precision using floating point expansions Front End 2016 Download Download
72. Digital Multiplierless Realization of Two-Coupled Biological Hindmarsh–Rose Neuron Model Front End 2016 Download Download
73. A Low Power Trainable Neuromorphic Integrated Circuit That Is Tolerant to Device Mismatch Back End 2016 Download Download
74. A 55-GHz-Bandwidth Track-and-Hold Amplifier in 28-nm Low-Power CMOS Back End 2016 Download Download
75. A Low-Power Incremental Delta–Sigma ADC for CMOS Image Sensors Back End 2016 Download Download
76. Low-Power ASK Detector for Low Modulation Indexes and Rail-to-Rail Input Range Back End 2016 Download Download
77. A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits Back End 2016 Download Download
78. PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors Back End 2016 Download Download
79. Low-Power Variation-Tolerant Nonvolatile Lookup Table Design Back End 2016 Download Download
80. Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design Back End 2016 Download Download
81. One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements Back End 2016 Download Download
82. Graph-Based Transistor Network Generation Method for Supergate Design Back End 2016 Download Download
83. A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell Back End 2016 Download Download
84. Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation Back End 2016 Download Download
85. Design for Testability of Sleep Convention Logic Back End 2016 Download Download
86. High - Throughput Finite Field Multipliers Using Redundant 8Basis For FPGA And ASIC Implementations Front End 2015 Download Download
87. A8 Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of DCT Front End 2015 Download Download
88. Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols Technique For DSRC Applications Front End 2015 Download Download
89. Obfuscating DSP Circuits Via High-Level Transformations Front End 2015 Download Download
90. Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding Front End 2015 Download Download
91. Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic Front End 2015 Download Download
92. Fault Tolerant Parallel Filters Based On Error Correction Codes Front End 2015 Download Download
93. A Synergetic Use Of Bloom Filters For Error Detection And Correction Front End 2015 Download Download
94. Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block Front End 2015 Download Download
95. Recursive Approach To The Design Of A Parallel Self-Timed Adder Front End 2015 Download Download
96. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic Front End 2015 Download Download
97. Fine-Grained Critical Path Analysis And Optimization For Area-Time Efficient Realization Of Multiple Constant Multiplications Front End 2015 Download Download
98. Scan Test Bandwidth Management For Ultralarge-Scale System-On-Chip Architectures Front End 2015 Download Download
99. Low-Power And Area-Efficient Shift Register Using Pulsed Latches Front End 2015 Download Download
100. Low-Power Programmable PRPG With Test Compression Capabilities Front End 2015 Download Download
101 One Minimum Only Trellis Decoder For Non – Binary Low - Density Parity - Check Codes Front End 2015 Download Download
102 A Low Complexity Scaling Method For The Lanczos Kernel In Fixed-Point Arithmetic Front End 2015 Download Download
103 Low-Latency High-Throughput Systolic Multipliers Over GF(2m) For NIST Recommended Pentanomials Front End 2015 Download Download
104 Efficient Coding Schemes For Fault-Tolerant Parallel Filters Front End 2015 Download Download
105 Partially Parallel Encoder Architecture For Long Polar Codes Front End 2015 Download Download
106 Novel Block-Formulation And Area-Delay - Efficient Reconfigurable Interpolation Filter Architecture For multi - Standard SDR Applications Front End 2015 Download Download
107 Algorithm And Architecture For A Low-Power Content-Addressable Memory Based On Sparse Clustered Networks Back End 2015 Download Download
108 A Self-Powered High-Efficiency Rectifier With Automatic Resetting Of Transducer Capacitance In Piezoelectric Energy Harvesting Systems Back End 2015 Download Download
109 Mixing Drivers In Clock-Tree For Power Supply NoiseReduction Back End 2015 Download Download
110. A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter For Sub-mW Energy Harvesting Applications Back End 2015 Download Download
111 An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator Front End 2014 Download Download
112 Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip Front End 2014 Download Download
113 Fast Radix-10 Multiplication Using Redundant BCD Codes Front End 2014 Download Download
114 A parallel radix-sort-based VLSI architecture for finding the first W maximum/minimum values Front End 2014 Download Download
115 Multifunction Residue Architectures for Cryptography Front End 2014 Download Download
116 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay Front End 2014 Download Download
117 32 Bit×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler Front End 2014 Download Download
118 Recursive Approach to the Design of a Parallel Self-Timed Adder Front End 2014 Download Download
119 Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications Front End 2014 Download Download
120 Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation Front End 2014 Download Download
121 Efficient Integer DCT Architectures for HEVC Front End 2014 Download Download
122 Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm Front End 2014 Download Download
123 A Method to Extend Orthogonal Latin Square Codes Front End 2014 Download Download
124 Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter Front End 2014 Download Download
125 On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays Front End 2014 Download Download
126 Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding Front End 2014 Download Download
127 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic Front End 2014 Download Download
128. Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes Front End 2014 Download Download
129 Area–Delay–Power Efficient Carry-Select Adder Front End 2014 Download Download
130 Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences Front End 2014 Download Download
131 Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement Front End 2014 Download Download
132 Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States Front End 2014 Download Download
133 Sharing Logic for Built-In Generation of Functional BroadsideTests Front End 2014 Download Download
134 A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits Back End 2014 Download Download
135 Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata Back End 2014 Download Download
136 Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator Back End 2014 Download Download
137 Digitally Controlled Pulse Width Modulator for On-Chip Power Management Back End 2014 Download Download
138 Statistical Analysis of MUX-Based Physical Unclonable Functions Back End 2014 Download Download
139 Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme Back End 2014 Download Download
140 Area-Delay Efficient Binary Adders in QCA Back End 2014 Download Download