An ISO 9001:2000 certified organization
  • Call: 040 - 4443 3434
  • Mail: ramu.krest@gmail.com

M.Tech-ECE-VLSI 2016-2017

 Download Project List

Sno

Projects List

Design

IEEE

Base Paper

Abstract

1. Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding Front End 2016 Download Download
2. Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation Front End 2016 Download Download
3. Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic Front End 2016 Download Download
4. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Front End 2016 Download Download
5. A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits Front End 2016 Download Download
6. On Efficient Retiming of Fixed-Point Circuits Front End 2016 Download Download
7. Concept, Design, and Implementation of Reconfigurable CORDIC Front End 2016 Download Download
8. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks Front End 2016 Download Download
9. Low-Power Parallel Chien Search Architecture Using a Two-Step Approach Front End 2016 Download Download
10. An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code Front End 2016 Download Download
11. Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression Front End 2016 Download Download
12. Multiple Constant Multiplication Algorithm for High-Speed and Low-Power Design Front End 2016 Download Download
13. Design and Analysis of Inexact Floating-Point Adders Front End 2016 Download Download
14. A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT Front End 2016 Download Download
15. A Modified Partial Product Generator for Redundant Binary Multipliers Front End 2016 Download Download
16. A Cellular Network Architecture With Polynomial Weight Functions Front End 2016 Download Download
17. A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO Front End 2016 Download Download
18. High Speed Hybrid Double Multiplication Architectures Using New Serial-Out Bit- Level Mastrovito Multipliers Front End 2016 Download Download
19. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication Front End 2016 Download Download
20. A High-Speed FPGA Implementation of an RSD-Based ECC Processor Front End 2016 Download Download
21. VLSI Design for Convolutive Blind Source Separation Front End 2016 Download Download
22. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels Front End 2016 Download Download
23. Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding Front End 2016 Download Download
24. Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers Front End 2016 Download Download
25. Hybrid LUT/Multiplexer FPGA Logic Architectures Front End 2016 Download Download
26. High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m) Front End 2016 Download Download
27. In-Field Test for Permanent Faults in FIFO Buffers of NOC Routers Front End 2016 Download Download
28. Performance/Power Space Exploration for Binary64 Division Units Front End 2016 Download Download
29. A High Throughput List Decoder Architecture for Polar Codes Front End 2016 Download Download
30. A Novel Coding Scheme for Secure Communications in Distributed RFID Systems Front End 2016 Download Download
31. Arithmetic algorithms for extended precision using floating point expansions Front End 2016 Download Download
32. Digital Multiplierless Realization of Two-Coupled Biological Hindmarsh–Rose Neuron Model Front End 2016 Download Download
33. A Low Power Trainable Neuromorphic Integrated Circuit That Is Tolerant to Device Mismatch Back End 2016 Download Download
34. A 55-GHz-Bandwidth Track-and-Hold Amplifier in 28-nm Low-Power CMOS Back End 2016 Download Download
35. A Low-Power Incremental Delta–Sigma ADC for CMOS Image Sensors Back End 2016 Download Download
36. Low-Power ASK Detector for Low Modulation Indexes and Rail-to-Rail Input Range Back End 2016 Download Download
37. A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits Back End 2016 Download Download
38. PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors Back End 2016 Download Download
39. Low-Power Variation-Tolerant Nonvolatile Lookup Table Design Back End 2016 Download Download
40. Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design Back End 2016 Download Download
41. One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements Back End 2016 Download Download
42. Graph-Based Transistor Network Generation Method for Supergate Design Back End 2016 Download Download
43. A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell Back End 2016 Download Download
44. Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation Back End 2016 Download Download
45. Design for Testability of Sleep Convention Logic Back End 2016 Download Download
46. High - Throughput Finite Field Multipliers Using Redundant Basis For FPGA And ASIC Implementations Front End 2015 Download Download
47. A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of DCT Front End 2015 Download Download
48. Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols Technique For DSRC Applications Front End 2015 Download Download
49. Obfuscating DSP Circuits Via High-Level Transformations Front End 2015 Download Download
50. Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding Front End 2015 Download Download
51. Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic Front End 2015 Download Download
52. Fault Tolerant Parallel Filters Based On Error Correction Codes Front End 2015 Download Download
53. A Synergetic Use Of Bloom Filters For Error Detection And Correction Front End 2015 Download Download
54. Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block Front End 2015 Download Download
55. Recursive Approach To The Design Of A Parallel Self-Timed Adder Front End 2015 Download Download
56. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic Front End 2015 Download Download
57. Fine-Grained Critical Path Analysis And Optimization For Area-Time Efficient Realization Of Multiple Constant Multiplications Front End 2015 Download Download
58. Scan Test Bandwidth Management For Ultralarge-Scale System-On-Chip Architectures Front End 2015 Download Download
59. Low-Power And Area-Efficient Shift Register Using Pulsed Latches Front End 2015 Download Download
60. Low-Power Programmable PRPG With Test Compression Capabilities Front End 2015 Download Download
61. One Minimum Only Trellis Decoder For Non – Binary Low - Density Parity - Check Codes Front End 2015 Download Download
62. A Low Complexity Scaling Method For The Lanczos Kernel In Fixed-Point Arithmetic Front End 2015 Download Download
63. Low-Latency High-Throughput Systolic Multipliers Over GF(2m) For NIST Recommended Pentanomials Front End 2015 Download Download
64. Efficient Coding Schemes For Fault-Tolerant Parallel Filters Front End 2015 Download Download
65. Partially Parallel Encoder Architecture For Long Polar Codes Front End 2015 Download Download
66. Novel Block-Formulation And Area-Delay - Efficient Reconfigurable Interpolation Filter Architecture For multi - Standard SDR Applications Front End 2015 Download Download
67. Algorithm And Architecture For A Low-Power Content-Addressable Memory Based On Sparse Clustered Networks Back End 2015 Download Download
68. A Self-Powered High-Efficiency Rectifier With Automatic Resetting Of Transducer Capacitance In Piezoelectric Energy Harvesting Systems Back End 2015 Download Download
69. Mixing Drivers In Clock-Tree For Power Supply Noise Reduction Back End 2015 Download Download
70. A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter For Sub-mW Energy Harvesting Applications Back End 2015 Download Download
71. An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator Front End 2014 Download Download
72. Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip Front End 2014 Download Download
73. Fast Radix-10 Multiplication Using Redundant BCD Codes Front End 2014 Download Download
74. A parallel radix-sort-based VLSI architecture for finding the first W maximum/minimum values Front End 2014 Download Download
75. Multifunction Residue Architectures for Cryptography Front End 2014 Download Download
76. Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay Front End 2014 Download Download
77. 32 Bit×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler Front End 2014 Download Download
78. Recursive Approach to the Design of a Parallel Self-Timed Adder Front End 2014 Download Download
79. Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications Front End 2014 Download Download
80. Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation Front End 2014 Download Download
81. Efficient Integer DCT Architectures for HEVC Front End 2014 Download Download
82. Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm Front End 2014 Download Download
83. A Method to Extend Orthogonal Latin Square Codes Front End 2014 Download Download
84. Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter Front End 2014 Download Download
85. On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays Front End 2014 Download Download
86. Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding Front End 2014 Download Download
87. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic Front End 2014 Download Download
88. Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes Front End 2014 Download Download
89. Area–Delay–Power Efficient Carry-Select Adder Front End 2014 Download Download
90. Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences Front End 2014 Download Download
91. Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement Front End 2014 Download Download
92. Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States Front End 2014 Download Download
93. Sharing Logic for Built-In Generation of Functional Broadside Tests Front End 2014 Download Download
94. A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits Back End 2014 Download Download
95. Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata Back End 2014 Download Download
96. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator Back End 2014 Download Download
97. Digitally Controlled Pulse Width Modulator for On-Chip Power Management Back End 2014 Download Download
98. Statistical Analysis of MUX-Based Physical Unclonable Functions Back End 2014 Download Download
99. Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme Back End 2014 Download Download
100. Area-Delay Efficient Binary Adders in QCA Back End 2014 Download Download