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B.Tech-ECE-VLSI ( Mini Projects ) 2017

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Front End Design(VHDL/Verilog HDL)


Projects List


1. Implementation of Dadda Algorithm and its applications Download
2. Area efficient Image Compression Technique using DWT Download
3. High speed and Area efficient Radix-8 Multiplier for DSP applications Download
4. Error Protection Scheme For Registers(Self Immunity Technique) Download
5. Design and implementation of LUT using APC-OMS Technique Download
6. Parallel prefix adders for cryptographic applications Download
7. Design and Implementation of DES Download
8. Synthesis Techniques for Pseudo-Random Built-In Self-Test Based on the LFSR Download
9. Power Optimization of Linear Feedback Shift Register LFSR) for Low Power BIST implemented in HDL Download
10. Area efficient concurrent error detection and correction for parallel filters Download
11. Design of Optimized Reversible Multiplier for High Speed DSP Application Download
12. Interfacing Synchronous and Asynchronous Domains for Open Core Protocol Download
13. Implementation of CRC on FPGA Download
14. Low power and area efficient Wallace tree multiplier using carry select adder with binary to excess-1 converter Download
15. Design of Anti-collision Technique for RFID UHF Tag using Verilog Download
16. Low Power Compressor Based MAC Architecture for DSP Applications Download
17. A Very Fast and Low Power Carry Select Adder Circuit Download
18. Multiplication Acceleration Through Twin Precision Download
19. Designing Efficient Online Testable Reversible Adders With New Reversible Gate Download
20. Performance of Low Power BIST Architecture for UART Download
21. Single phase clock distribution using VLSI technology for low power Download
22. High Speed FPGA implementation of FIR Filters for DSP Applications Download
23. Implementation of an Efficient Multiplier based on Urdhva Tiryakbhyam Sutra Download
24. LUT Optimization for Memory-Based Computation Download
25. Design and implementation of Floating Point Multiplier based on Vedic Multiplication Technique Download
26. Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA Download
27. Constant and high speed adder design using QSD number system Download
28. FPGA implementation of multi operand redundant adders Download
29. A Novel Approach for parallel CRC generation for High Speed Application Download
30. A Common Boolean Logic(CBL) implementation for modified CSLA Download
31. Implementation of Bus Bridge between AHB and OCP Download
32. An Efficient Implementation of Floating Point Multiplier Download
33. A New Approach To Design Fault Coverage Circuit With Efficient Hardware Utilization for Testing Applications Download
34. Area Efficient parallel FIR Digital Filter Structures for Symmetric Convolution based on Fast FIR Algorithm Download
Back End Design
35. Recursive Approach To The Design of A Parallel Self-Timed Adder Download
36. Low power area efficient ALU with low power full adder Download
37. Comparative analysis and optimization of active power and delay of 1-bit full adder at 45nm technology Download
38. Statistical Analysis of MUX-Based Physical Unclonable Functions Download
39. Low power 6T SRAM design Download
40. Realization of Basic Gates Using MUX in CMOS Designs Download
41. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator Download
42. CMOS Full-Adders for Energy-Efficient Arithmetic Applications Download
43. Low power design of Flip flop using reversible logic Download
44. Area Efficient ROM-Embedded SRAM Cache Download
45. Low power design of ripple carry adder Download