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Front End Design(VHDL/Verilog HDL) |
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Projects List
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Abstract
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1. |
Implementation of Dadda Algorithm and its applications |
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2. |
Area efficient Image Compression Technique using DWT |
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3. |
High speed and Area efficient Radix-8 Multiplier for DSP applications |
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4. |
Error Protection Scheme For Registers(Self Immunity Technique) |
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5. |
Design and implementation of LUT using APC-OMS Technique |
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6. |
Parallel prefix adders for cryptographic applications |
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7. |
Design and Implementation of DES |
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8. |
Synthesis Techniques for Pseudo-Random Built-In Self-Test Based on the LFSR |
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9. |
Power Optimization of Linear Feedback Shift Register LFSR) for Low Power BIST implemented in HDL |
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10. |
Area efficient concurrent error detection and correction for parallel filters |
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11. |
Design of Optimized Reversible Multiplier for High Speed DSP Application |
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12. |
Interfacing Synchronous and Asynchronous Domains for Open Core Protocol |
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13. |
Implementation of CRC on FPGA |
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14. |
Low power and area efficient Wallace tree multiplier using carry select adder with binary to excess-1 converter |
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15. |
Design of Anti-collision Technique for RFID UHF Tag using Verilog |
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16. |
Low Power Compressor Based MAC Architecture for DSP Applications |
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17. |
A Very Fast and Low Power Carry Select Adder Circuit |
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18. |
Multiplication Acceleration Through Twin Precision |
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19. |
Designing Efficient Online Testable Reversible Adders With New Reversible Gate |
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20. |
Performance of Low Power BIST Architecture for UART |
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21. |
Single phase clock distribution using VLSI technology for low power |
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22. |
High Speed FPGA implementation of FIR Filters for DSP Applications |
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23. |
Implementation of an Efficient Multiplier based on Urdhva Tiryakbhyam Sutra |
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24. |
LUT Optimization for Memory-Based Computation |
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25. |
Design and implementation of Floating Point Multiplier based on Vedic Multiplication Technique |
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26. |
Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA |
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27. |
Constant and high speed adder design using QSD number system |
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28. |
FPGA implementation of multi operand redundant adders |
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29. |
A Novel Approach for parallel CRC generation for High Speed Application |
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30. |
A Common Boolean Logic(CBL) implementation for modified CSLA |
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31. |
Implementation of Bus Bridge between AHB and OCP |
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32. |
An Efficient Implementation of Floating Point Multiplier |
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33. |
A New Approach To Design Fault Coverage Circuit With Efficient Hardware Utilization for Testing Applications |
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34. |
Area Efficient parallel FIR Digital Filter Structures for Symmetric Convolution based on Fast FIR Algorithm |
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Back End Design |
35. |
Recursive Approach To The Design of A Parallel Self-Timed Adder |
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36. |
Low power area efficient ALU with low power full adder |
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37. |
Comparative analysis and optimization of active power and delay of 1-bit full adder at 45nm technology |
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38. |
Statistical Analysis of MUX-Based Physical Unclonable Functions |
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39. |
Low power 6T SRAM design |
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40. |
Realization of Basic Gates Using MUX in CMOS Designs |
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41. |
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator |
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42. |
CMOS Full-Adders for Energy-Efficient Arithmetic Applications |
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43. |
Low power design of Flip flop using reversible logic |
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44. |
Area Efficient ROM-Embedded SRAM Cache |
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45. |
Low power design of ripple carry adder |
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