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B.Tech-ECE-VLSI 2017-2018

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Projects List

IEEE Year

Abstract

Base Paper

Front End Design(VHDL/Verilog HDL)
1. Design And Implementation Of A Novel PRPG for Low Power Applications 2017 Download Download
2. A New Algorithm For Multiple Constant Multiplications With Low Power Consumption 2017 Download Download
3. Design of MAC Unit For DSP Applications Using Verilog HDL 2017 Download Download
4. Floating-Point Butterfly Architecture Based On Multi Operand Adders 2017 Download Download
5. VLSI Architecture For Montgomery Modular Multiplication Algorithm By Using Pasta Adder 2017 Download Download
6. Pre encoded Multiplier Architecture Based On NR4SD Encoding Technique For DSP Applications 2017 Download Download
7. Design And Implementation Of High Speed Accelerator Using Carry Save Adder 2017 Download Download
8. VLSI Design Of A Novel Pre Encoding Multiplier Using DADDA Multiplier 2017 Download Download
9. Fault Tolerant Parallel Filters design For Communication Applications 2017 Download Download
10. A Transparent Test Technique For Detection Of Faults In FIFO Buffers Of NOC Routers 2017 Download Download
11. Design Of 16-Bit Multiplier Using Modified Gate Diffusion Input Logic 2017 Download Download
12. An Optimized Implementation Of IEEE-754 Floating Point Multiplier For DSP Applications 2017 Download Download
13. Efficient Architecture For Processing Of Two Independent Data Streams Using Radix-2 FFT 2017 Download Download
14. Implementation & Design Of Low Power Multiplier Using Fixed Width Replica Redundancy Block 2017 Download Download
15. High Throughput DA-Based Fir Filter For FPGA Implementation 2017 Download Download
16. Low Power And Area Efficient Wallace Tree Multiplier Using Carry Select Adder With Binary To Excess-1 Converter 2016 Download Download
17. VLSI Design Of High Speed Vedic Multiplier For FPGA Implementation 2016 Download Download
18. A Review On Power Optimized TPG Using LP-LFSR For Low Power BIST 2016 Download Download
19. FPGA Based Hardware Implementation Of AES Rijndael Algorithm For Encryption And Decryption 2016 Download Download
20. A Modified Partial Product Generator For Redundant Binary Multipliers 2016 Download Download
21. Pipeline And Parallel Processor Architecture For Fast Computation Of 3D-DWT Using Modified Lifting Scheme 2016 Download Download
22. Hybrid LUT/Multiplexer FPGA Logic Architectures 2016 Download Download
23. Multi-Bit Flip-Flop Generation Considering Multicorner Multi-Mode Timing Constraint 2016 Download Download
24. Carry Speculative Adder With Variable Latency For Low Power VLSI 2016 Download Download
25. A Synergetic Use Of Bloom Filters For Error Detection And Correction 2015 Download Download
26. Fault Tolerant Parallel Filters Based On Error Correction Codes 2015 Download Download
27. Obfuscating DSP Circuits Via High-Level Transformations 2015 Download Download
28. A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of DCT 2015 Download Download
29. Scan Test Bandwidth Management For Ultra large-Scale System-On-Chip Architectures 2015 Download Download
30. Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols Technique For DSRC Applications 2015 Download Download
31. Low-Power And Area-Efficient Shift Register Using Pulsed Latches 2015 Download Download
32. High-Throughput Finite Field Multipliers Using Redundant Basis For FPGA And ASIC Implementations 2015 Download Download
33. An Efficient Constant Multiplier Architecture Based On Vertical-Horizontal Binary Common Sub-Expression Elimination Algorithm For Reconfigurable FIR Filter Synthesis 2015 Download Download
34. Low Delay Single Symbol Error Correction Codes Based On Reed Solomon Codes 2015 Download Download
35. High-Throughput Finite Field Multipliers Using Redundant Basis For FPGA And ASIC Implementations 2015 Download Download
36. Recursive Approach To The Design of a Parallel Self-Timed Adder 2015 Download Download
37. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic 2015 Download Download
38. A Low Complexity Scaling Method For The Lanczos Kernel In Fixed-Point Arithmetic 2015 Download Download
39. Design & Analysis of 16 bit RISC Processor Using low Power Pipelining 2015 Download Download
40. Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications 2015 Download Download
Back End Design
41. A New VLSI Architecture Of Power Efficient Nonvolatile Lookup Table Design Based On RRAM 2017 Download Download
42. Low Power Area Efficient ALU With A Novel Full Adder 2016 Download Download
43. Mixing Drivers In Clock-Tree For Power Supply Noise Reduction 2015 Download Download
44. A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter For Sub-Mw Energy Harvesting Applications 2015 Download Download
45. Algorithm And Architecture For A Low-Power Content-Addressable Memory Based On Sparse Clustered Networks 2015 Download Download
46. Statistical Analysis Of MUX-Based Physical Unclonable Functions 2015 Download Download
47. Analysis And Design Of A Low-Voltage Low-Power Double-Tail Comparator 2015 Download Download
48. Digitally Controlled Pulse Width Modulator For On-Chip Power Management 2015 Download Download
49. A Multiobjective Optimization Based Fast And Robust Design Methodology For Low Power And Low Phase Noise Current Starved VCO 2015 Download Download
50. Area Efficient Rom-Embedded SRAM Cache 2015 Download Download