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B.Tech-ECE-VLSI 2019-2020

 Download Project List

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Projects List

IEEE Year

Abstract

Base Paper

Front End Design(VHDL/Verilog HDL)
1. A Low-Power Parallel Architecture for Linear Feedback Shift Registers Download Download
2. FSM based High Speed VLSI Architecture for DBUTVF Algorithm Download Download
3. Machine Learning based Power Efficient Approximate 4:2 Compressors for Imprecise Multipliers Download Download
4. A Double Error Correction Code for 32-bit Data Words with Efficient Decoding Download Download
5. A Low Power Binary Square Rooter using Reversible Logic Download Download
6. A New Logic for Implementation of Digital Error Correction Block Download Download
7. Fast & Energy Efficient Binary to BCD Converter with Complement Based Logic Design (CBLD) for BCD Multipliers Download Download
8. Design of 32-bit MIPS ALU by Efficient Adders Download Download
9. FPGA Based 64-Bit Low Power RISC Processor Using Verilog HDL Download Download
10. Area and Time Efficient Square Architecture Download Download
11. Modified Binary Multiplication Circuit Based On Vedic Mathematics Download Download
12. An Efficient Design Of 16 Bit MAC Unit Using Vedic Mathematics Download Download
13. 16 bit power efficient carry select adder Download Download
14. Dual-quality 4:2 Compressors For Utilizing In Dynamic Accuracy Configurable Multipliers Download Download
15. Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding Download Download
16. Design of Multiplier less Multiple Constant Multiplication for Convolution Circuits Download Download
17. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Download Download
18. Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block Download Download
19. A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits Download Download
Back End Design(VHDL/Verilog HDL)
20. Analysis of Adiabatic flip-flops for Ultra Low Power Applications. Download Download
21. Design of Low-Power High-Performance 24 and 416 Mixed-Logic Line Decoders Download Download
22. Low power area efficient ALU with low power full adder Download Download