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B.Tech-ECE-VLSI 2018-2019

 Download Project List

Sno

Projects List

IEEE Year

Abstract

Base Paper

Front End Design(VHDL/Verilog HDL)
1. VLSI Design Of Low-Cost And High-Precision Fixed-Point Reconfigurable FFT Processors 2018 Download Download
2. Unbiased Rounding for HUB Floating-point Addition 2018 Download Download
3. A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design 2018 Download Download
4. Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction 2018 Download Download
5. A Low-Power Yet High-Speed Configurable Adder for Approximate Computing 2018 Download Download
6. The Design and Implementation of Multi – Precision Floating Point Arithmetic Unit Based on FPGA 2018 Download Download
7. Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers 2018 Download Download
8. Efficient Modular Adders based on Reversible Circuits 2018 Download Download
9. Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption 2018 Download Download
10. Design of 5 port router for network on chip using FPGA 2018 Download Download
11. Design And Implementation Of A Novel PRPG for Low Power Applications 2017 Download Download
12. Design of MAC Unit For DSP Applications Using Verilog HDL 2017 Download Download
13. Floating-Point Butterfly Architecture Based On Multi Operand Adders 2017 Download Download
14. VLSI Architecture For Montgomery Modular Multiplication Algorithm By Using Pasta Adder 2017 Download Download
15. Pre encoded Multiplier Architecture Based On NR4SD Encoding Technique For DSP Applications 2017 Download Download
16. Design And Implementation Of High Speed Accelerator Using Carry Save Adder 2017 Download Download
17. A Transparent Test Technique For Detection Of Faults In FIFO Buffers Of NOC Routers 2017 Download Download
18. Design Of 16-Bit Multiplier Using Modified Gate Diffusion Input Logic 2017 Download Download
19. An Optimized Implementation Of IEEE-754 Floating Point Multiplier For DSP Applications 2017 Download Download
20. Efficient Architecture For Processing Of Two Independent Data Streams Using Radix-2 FFT 2017 Download Download
21. High Throughput DA-Based Fir Filter For FPGA Implementation 2017 Download Download
22. Low Power And Area Efficient Carry Select Adder With Binary To Excess-1 Converter 2016 Download Download
23. VLSI Design Of High Speed Vedic Multiplier For FPGA Implementation 2016 Download Download
24. A Review On Power Optimized TPG Using LP-LFSR For Low Power BIST 2016 Download Download
25. FPGA Based Hardware Implementation Of AES Rijndael Algorithm For Encryption And Decryption. 2016 Download Download
26. A Modified Partial Product Generator For Redundant Binary Multipliers 2016 Download Download
27. Pipeline And Parallel Processor Architecture For Fast Computation Of 3D-DWT Using Modified Lifting Scheme 2016 Download Download
28. Hybrid LUT/Multiplexer FPGA Logic Architectures 2016 Download Download
29. A Synergetic Use Of Bloom Filters For Error Detection And Correction 2015 Download Download
30. Fault Tolerant Parallel Filters Based On Error Correction Codes 2015 Download Download
31. High-Throughput Finite Field Multipliers Using Redundant Basis For FPGA And ASIC Implementations 2015 Download Download
32. Recursive Approach To The Design of a Parallel Self-Timed Adder 2015 Download Download
33. Low Delay Single Symbol Error Correction Codes Based On Reed Solomon Codes 2015 Download Download
Back End Design
34. Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates 2018 Download Download
35. Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder 2018 Download Download
36. Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders. 2017 Download Download
37. Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design. 2017 Download Download
38. A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell. 2017 Download Download
39. Low power 6T SRAM design 2016 Download Download
40. Algorithm And Architecture For A Low-Power Content-Addressable Memory Based On Sparse Clustered Networks 2015 Download Download